Gaming Partners International Corporation announced that it will unveil the latest in its RFID table applications at International Gaming Expo 2010, held in London on Jan. 26-28.
GPI’s presentation will feature its latest developments in furniture design, roulette and baccarat reader displays, and new product lines in currency and playing cards to compliment is its gaming tables, dice, playing cards, table layouts and accessories.
To improve performance in casino cages GPI plan to highlight an RFID cage application. The company has a new countertop reader that works in three dimensions, enabling the cage operator to accurately read chips whether they are in stacks, in chip racks or in a pile. GPI is also introducing its integrated RFID roulette application, which monitors and tracks bets, game activity and chip change operations automatically.
Also being presented is GPI’s RFIDPoker, developed to improve accuracy and increase the speed of various actions on the poker table. Able to be fitted on any poker table, GPI’s RFIDPoker works with RFID chips to provide error-free, automatic and constant reading of the poker pot, calculates charges and rakes, and provides essential data and statistics such as game analysis, table performances, round-ups lists, and daily totals.
RFIDPoker further helps to speed up the game and has proven to increase hands per hour by as much as 30%, improving revenues for casinos, and reducing wait times for players both at the game and waiting for a table.
GPI is also working on a new table application that interfaces with JCM bill authenticators and the chip trays to allow casino personnel to get a real-time status of the cash and chip currency at the table. This application utilizes a built-in display that allows for fills/credits management, chip authentication and tracking, and reading of bets for calculations based on game play, all directly at the table.
The new readers and application software hope to bring improved security of casino currency, increased speed of play at gaming tables and the elimination of error in chip counts and calculations.